1. Field of the Invention
The present invention relates to a semiconductor memory device such as DRAM (Dynamic Random Access Memory), and more particularly to a refresh control method for controlling the refresh operation in a semiconductor memory device that includes a memory cell array that is constituted by a plurality of mats equipped with normal word lines and redundant word lines.
2. Description of the Related Art
DRAMs store data by accumulating a charge in capacitors and therefore require refresh operations to be performed at a fixed cycle due to the leakage of the capacitor charge over the passage of time. These refresh operations are performed by successively activating word lines, reading the data of module cells that are connected to the activated word lines, amplifying the difference in potential by means of a sense amplifier, and rewriting to the original memory cells.
For example, refreshing a 64-kbits memory cell by means of a refresh command necessitates the input of 4000 (=256 Mbits/64 kbits) refresh commands to refresh all of the memory cells of a 256-Mbits semiconductor memory device. If refresh commands are applied at intervals of 7.8 xcexcs, the time required to refresh all memory cells (hereinbelow referred to as the xe2x80x9crefresh cyclexe2x80x9d) 7.8 xcexcsxc3x974 k=32 ms. If the storage capacity in such a semiconductor memory device is increased to, for example, 512 Mbits, 8K refresh operations, i.e., 64 ms, is required to refresh all memory cells.
Due to the increase in storage capacity of semiconductor memory devices in recent years, however, designs for miniaturization of patterns have resulted in a decrease in the capacitance of capacitors for storing data. In addition, designs in which the operating voltage is lowered in order to increase operating speed have resulted in a lowering of the voltage that is applied to capacitors. Also, since the amount of charge that is stored in capacitors is determined as the product of the capacitance of the capacitors and the applied voltage, recent years have seen a downward trend in the amount of charge that is accumulated in capacitors in semiconductor memory devices. Failure to carry out the refresh operation before the disappearance of the charge that is stored in capacitors results in the destruction of the data that are held, and it has therefore been necessary in recent years to shorten the refresh cycle in semiconductor memory devices. Thus, when the storage capacity is increased from 256 Mbits to 512 Mbits, the refresh cycle must be kept the same as for the 256-Mbit storage capacity.
When the refresh operation is carried out in 32 ms for all memory cells of 512 Mbits, the above-described object can be achieved by changing the interval for inputting refresh commands from 7.8 xcexcs to 3.9 xcexcs, or to one-half the original interval. In actual DRAM control, however, processing for data reading and writing is also performed in addition to the refresh operation, and an increase in processing for refresh operations therefore causes the speed of data reading and writing to fall, and the interval for performing processing for refresh operations therefore cannot be made shorter than 7.8 xcexcs.
To satisfy all of these conditions, the refresh operation for all memory cells of 512 Mbits must be carried out at a refresh cycle of 32 ms with the interval for the input of refresh commands kept at 7.8 xcexcs.
Here, an external 8K Ref/internal 4K Ref standard has been adopted in the DDR (Double Data Rate) II mode that has been investigated by JEDEC (Joint Electron Device Engineering Council). As shown in FIG. 1a, this external 8K Ref/internal 4K Ref standard is a standard in which, if all memory cells (512 Mbits) are refreshed by executing 8K (8192) refresh commands in 64 ms in the prior art, all memory cells (512 Mbits) are refreshed in 32 ms by refresh commands that are applied from the outside at the same cycle as in the prior art, i.e., by the input of 4K refresh commands.
Two methods can be considered when putting this external 8K Ref/internal 4K Ref standard into practice: a method as shown in FIG. 1b in which the refresh operation is carried out for twice as many word lines as the prior art by one refresh command; and a method as shown in FIG. 1c in which two refresh operations are performed serially within a chip by a single refresh command.
However, in a typical semiconductor memory device, redundant memory cells are supplied to provide a remedy for defective cells. Replacing word lines that contain defective memory cells with redundant word lines can save the entire semiconductor memory device from being rendered defective. However, these redundant word lines raise problems when the methods shown in FIGS. 1b and 1c are used.
The following explanation regards a case in which one memory cell array is constituted by 16 mats, each mat being made up by 512 word lines and 8 redundant word lines. FIG. 2 shows the memory cell array of a semiconductor memory device of this configuration. The memory cell array shown in this FIG. 2 is made up of 16 mats 100-1015, each of mats 100-1015 being made up of 512 word lines and 8 redundant word lines, and each of mats 100-1015 being provided with a respective sense amplifier 90-915. Redundant word lines are provided in a dispersed arrangement on each mat rather than in a concentrated arrangement because the failure of memory cells generally does not occur randomly but tends to occur in groups, resulting from, for example, the admixture of impurities in the process of fabricating the semiconductor memory device.
In a semiconductor memory device of this configuration, 64 bits of memory cells are refreshed by the selection of one word line. As a result, activating (512+8)xc3x9716=8320 word lines one at a time enables refreshing of all memory cells.
In contrast to the semiconductor memory device of this configuration, the external 8K Ref/internal 4K Ref standard can be realized if, when attempting to refresh 128 bits, i.e., twice the number of memory cells as in the prior art, by one refresh command, two word lines are activated and refreshed by the input of one refresh command as described in the foregoing explanation and as shown in FIG. 1b. In a semiconductor memory device that contains the memory cell array shown in FIG. 2, however, each of mats 100-1015 share sense amplifiers 90-916, and when two word lines are simultaneously activated in the same mat, the stored data are destroyed.
In this type of semiconductor memory device, moreover, the replacement of any redundant word line and any normal word line in the same memory cell array is enabled in order to raise the replacement efficiency. For example, the configuration allows a word line of mat 101 to be replaced by a redundant word line of mat 1015. When such replacement of defective word lines and redundant lines that exceeds the range of one mat is performed, the activation of a normal word line within a particular mat is in actuality the activation of a redundant word line in a different mat. As a result, even though two word lines that belong to different mats are to be selected and activated to carry out a refresh operation, in some cases, two word lines in the same mat may be activated.
For example, as shown in FIG. 3, we consider a case in which, in order to simultaneously activate and refresh two word lines through the input of one refresh command, a method is employed of successively activating normal word lines having row addresses that are shifted by 4096, i.e., normal word line 0 and normal word line 4096, normal word line 1 and normal word line 4097, and so on. In such a case, word line 0 belonging to mat 100 is replaced by redundant word line R64 belonging to mat 108, and word line 8191 belonging to mat 1015 is replaced by redundant word line R63 belonging to mat 107. In this case, the intended simultaneous activation of normal word line 0 and normal word line 4096 actually results in the simultaneous activation of normal word line 4096 and redundant word line R64, whereby two word lines in mat 108 are simultaneously activated and data are destroyed. Further, the intended simultaneous activation of normal word line 4095 and normal word line 8191 actually results in the simultaneous activation of normal word line 4095 and redundant word line R63, whereby two word lines in mat 107 are simultaneously activated and data are destroyed.
Alternatively, the method shown in FIG. 1c can be considered in which the external 8K Ref/internal 4K Ref standard is realized by performing two serial refresh operations in a chip by means of one refresh command.
However, as described in the foregoing explanation, when the replacement of a defective word line and redundant word line exceeds the range of the same mat, the serial activation of two word lines necessitates the consideration of consecutive activation of word lines in the same mat.
For example, as shown in FIG. 4, in order to perform a refresh operation by consecutively activating two word lines by the input of one refresh command, the use of a method can be considered in which combinations of normal word lines having row addresses that are separated by 4096 are successively activated, e.g., normal word line 0 and normal word line 4096, normal word line 1 and normal word line 4097, and so on. In such a case, word line 0 belonging to mat 100 is replaced by redundant on word line R64 belonging to mat 108, and word line 8191 belonging to mat 1015 is replaced by redundant word line R63 belonging to mat 107. In this case, when normal word line 0 and normal word line 4096 are to be consecutively activated, in actuality, normal word line 4096 and redundant word line R64 are consecutively activated, whereby two word lines in mat 108 are consecutively activated. In addition, the intended consecutive activation of normal word line 4095 and normal word line 8191 actually results in the consecutive activation of normal word line 4095 and redundant word line R63, whereby two word lines in mat 107 are consecutively activated.
When word lines that share a sense amplifier are to be consecutively activated, activation of the succeeding word line cannot be realized until the bit line selection, bit line amplification by the sense amplifier, and bit line precharging have been carried out for the previous word line.
In other words, the time tRFC for one refresh operation is 2xc3x97(internal tRAS (Row Address Strobe)+internal tRP (RAS Precharge) as shown in FIG. 5, which is twice the tRFC of the 8K Ref standard, and this results in the same problem that was encountered when the interval of input of refresh commands is set to 3.9 xcexcs from 7.8 xcexcs, i.e., a decrease in operating speeds for operations other than refresh, such as for reading and writing data.
It is an object of the present invention to provide a semiconductor memory device and a refresh control method that can realize the external 8K Ref/internal 4K Ref standard without damaging stored data, and moreover, without increasing the time tRFC for one refresh operation.
To achieve the above-described object, the semiconductor memory device of the present invention is a semiconductor memory device having a memory cell array that is constituted by a plurality of mats that are each provided with normal word lines and redundant word lines, the semiconductor memory device being provided with an X-system control circuit, a refresh counter, a remedy circuit, and an X-decoder.
Upon the input of a refresh command instructing a refresh operation, the X-system control circuit generates and outputs a refresh activation signal that indicates the start of a refresh operation, outputs a redundancy non-access signal for preventing replacement by redundant word lines when refreshing normal word lines, and outputs a redundancy access signal for preventing activation of normal word lines when refreshing redundant word lines.
Upon the input of a refresh activation signal from the X-system control circuit, the refresh counter successively generates and outputs addresses for selecting two normal word lines that do not belong to the same mat with each input of a refresh activation signal, and after having generated addresses for selecting all normal word lines, successively generates addresses for selecting two redundant word lines that do not belong to the same mat with each input of a refresh activation signal and outputs these generated addresses as refresh addresses.
The remedy circuit activates a normal word line selection signal for enabling selection of normal word lines when the redundancy non-access signal is active, and activates a redundant word line selection signal for enabling selection of redundant word lines when the redundancy access signal is active.
The X-decoder simultaneously activates two normal word lines instructed by the refresh addresses when the normal word line selection signal is active, and simultaneously activates two redundant word lines that are instructed by the refresh addresses when the redundant word line selection signal is active.
According to the present invention, refreshing of normal word lines and refreshing of a redundant word lines are each performed while preventing replacement of normal word lines by redundant word lines, and as a result, two word lines in the same mat will not be simultaneously activated even when two word lines are refreshed by one refresh command. Thus, the external 8K Ref/internal 4K Ref standard can be realized without destroying stored data.
Another semiconductor memory device of the present invention is similarly provided with an X-system control circuit, a refresh counter, a remedy circuit, and an X-decoder.
Upon the input of a refresh command instructing a refresh operation, the X-system control circuit generates and outputs two refresh activation signals that indicate the start of refresh operations, outputs a redundancy non-access signal for preventing replacement by redundant word lines when refreshing normal word lines, and outputs a redundancy access signal for preventing activation of normal word lines when refreshing redundant word lines.
Upon the input of a refresh activation signal from the X-system control circuit, the refresh counter successively generates and outputs addresses for selecting normal word lines such that preceding and succeeding addresses do not belong to the same mat with each input of a refresh activation signal, and after having generated addresses for selecting all normal word lines, successively generates addresses for selecting redundant word lines such that preceding and succeeding addresses do not belong to the same mat with each input of a refresh activation signal and outputs these generated addresses-as refresh addresses.
The remedy circuit activates a normal word line selection signal for enabling selection of normal word lines when the redundancy non-access signal is active, and activates a redundant word line selection signal for enabling selection of redundant word lines when the redundancy access signal is active.
The X-decoder consecutively activates two normal word lines that are instructed by the refresh addresses when the normal word line selection signal is active, and consecutively activates two redundant word lines that are instructed by the refresh addresses when the redundant word line selection signal is active.
According to the present invention, the refreshing of is normal word lines and the refreshing of redundant word line are each carried out while preventing replacement of normal word lines by redundant word lines, whereby two word lines in the same mat will not be consecutively activated even when two word lines are consecutively refreshed by one refresh command. As a result, after activating a particular word line, a next word line can be activated without waiting for bit-line amplification and bit-line precharging by a sense amplifier, i.e., by allowing processing to overlap. In this way, the external 8K Ref/internal 4K Ref standard can be realized without causing the time tRFC for one refresh operation to become double the tRFC of the 8K Ref standard. Further, the amount of refreshing that can be performed simultaneously is the same as in the prior art, and the array noise therefore does not increase compared to a prior-art semiconductor memory device.
The above and other objects, features, and advantages of the present invention will become apparent from the following description with reference to the accompanying drawings, which illustrate examples of the present invention.